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tx working in theory, but must be optimized

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This commit is contained in:
TerraMaster85 2024-12-16 22:58:30 -05:00
parent b8086e19ba
commit bbcb3a6b2d
4 changed files with 21 additions and 21 deletions
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4
src/audio_transmitter/mod.rs
View file

@ -148,8 +148,8 @@ where
*outgoing = match channel.try_recv() {
Ok(sample) => sample.to_sample::<T>(),
Err(_) => {
//warn!("rx_for_wire has no samples for us! carrier dead!");
//warn!("are we able to produce samples quickly enough? CPU OK?");
warn!("rx_for_wire has no samples for us! carrier dead!");
warn!("are we able to produce samples quickly enough? CPU OK?");
T::EQUILIBRIUM
}
};

26
src/dsp_common/carrier.rs
View file

@ -19,39 +19,37 @@ pub trait Carrier {
impl Carrier for TwoStateCarrier {
fn byte_into_fsk_samples(&mut self, byte: &u8) -> Vec<PcmSample> {
let mut bits: Vec<u8> = vec![];
let mut bits: [u8; 8] = [0, 0, 0, 0, 0, 0, 0, 0];
let mut out: Vec<i64> = vec![];
// MSb first
bits.push((byte ) & 1);
bits.push((byte >> 1) & 1);
bits.push((byte >> 2) & 1);
bits.push((byte >> 3) & 1);
bits.push((byte >> 4) & 1);
bits.push((byte >> 5) & 1);
bits.push((byte >> 6) & 1);
bits.push((byte >> 7) & 1);
bits[0] = (byte ) & 1;
bits[1] = (byte >> 1) & 1;
bits[2] = (byte >> 2) & 1;
bits[3] = (byte >> 3) & 1;
bits[4] = (byte >> 4) & 1;
bits[5] = (byte >> 5) & 1;
bits[6] = (byte >> 6) & 1;
bits[7] = (byte >> 7) & 1;
for (i, bit) in bits.into_iter().enumerate() {
if bit == 0 {
trace!("low bit {} in fsk code", i);
while (self.phase_low) < self.sample_rate / self.freq_low {
trace!("low bit gen sin");
out.push((self.phase_low * TAU * self.freq_low / self.sample_rate).sin().to_sample::<i64>());
self.phase_low += 1.0;
}
self.phase_low = self.phase_low % self.sample_rate;
self.phase_low = self.phase_low % (self.sample_rate / self.freq_high);
} else if bit == 1 {
trace!("high bit {} in fsk code", i);
while (self.phase_high) < self.sample_rate / self.freq_high {
trace!("high bit gen sin");
out.push((self.phase_high * TAU * self.freq_low / self.sample_rate).sin().to_sample::<i64>());
self.phase_high += 1.0;
}
self.phase_high = self.phase_high % self.sample_rate;
self.phase_high = self.phase_high % (self.sample_rate / self.freq_low);
}
}
trace!("FSK calculations turned up {:?}", &out);
//trace!("FSK calculations turned up {:?}", &out);
out
}
}

10
src/dsp_outb/mod.rs
View file

@ -17,8 +17,8 @@ pub async fn dsp_outb_main(
trace!("pcm_outb task started");
let carrier_phase = 0_f64;
let carrier_low = 2400;
let carrier_high = 2500;
let carrier_low = 240;
let carrier_high = 250;
// TODO: fetch real sample rate
let mut carrier = TwoStateCarrier::new(carrier_low, carrier_high, 384000);
@ -27,8 +27,10 @@ pub async fn dsp_outb_main(
let eth_frame = match rx_for_mod.try_recv() {
Ok(x) => x,
Err(TryRecvError::Empty) => {
tx_for_wire.send(i64::EQUILIBRIUM).await?;
continue;
trace!("no eth frames to modulate!");
//tx_for_wire.send(i64::EQUILIBRIUM).await?;
//continue;
vec![0, 0, 0, 0, 0, 0, 0, 0,]
}
Err(TryRecvError::Disconnected) => {
Err(anyhow::Error::msg(

2
src/main.rs
View file

@ -57,7 +57,7 @@ async fn main() -> Result<()> {
let (tx_for_eth_inb, rx_for_eth_inb) =
unbounded_channel::<RawEthFrameMessage>();
let (tx_for_mod, rx_for_mod) = channel::<RawEthFrameMessage>(1024);
let (tx_for_wire, rx_for_wire) = channel::<PcmSampleMessage>(1);
let (tx_for_wire, rx_for_wire) = channel::<PcmSampleMessage>(1024);
trace!("starting listener for audio on wire");
let audio_in_stream = audio_receiver_main(tx_for_demod, &cpal_input)