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Obliterate interrupt code for rewriting

This commit is contained in:
c0repwn3r 2022-05-09 10:24:54 -04:00
parent 881886c375
commit abf0b2bdc1
Signed by: core
GPG Key ID: FDBF740DADDCEECF
11 changed files with 0 additions and 484 deletions
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bin/kernel.bin
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kernel.elf Executable file
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obj/kernel/platform/interrupts/idt.o
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obj/kernel/platform/interrupts/int.o
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14
src/kernel/kernel.c
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@ -48,18 +48,4 @@ void main() {
print_str("This program is provided \"as-is\" and no express or implied warranty is provided.\n");
print_str("The full license can be found at /sys/LICENCE on this system or ./LICENCE in the source tree.\n");
print_str("Initializing interrupts...\n");
isr_setup();
kernel_msg_ok("isr setup done\n");
// Test interrupts
__asm__ __volatile__("int $2");
kernel_msg_ok("int 2 not failed");
__asm__ __volatile__("int $3");
__asm__ __volatile__("int $2");
__asm__ __volatile__("int $3");
__asm__ __volatile__("int $2");
__asm__ __volatile__("int $3");
kernel_msg_ok("interrupt test completed\n");
}

20
src/kernel/platform/interrupts/idt.c
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@ -1,20 +0,0 @@
#include "idt.h"
#include "../../util.h"
idt_gate_t idt[IDT_ENTRIES];
idt_pointer_t idt_ptr;
void idt_set_gate(int n, u32 handler_addr) {
idt[n].low_offset = low16(handler_addr);
idt[n].sel = KERNEL_CS;
idt[n].reserved = 0;
idt[n].flags = 0x8E;
idt[n].high_offset = high16(handler_addr);
}
void idt_set() {
idt_ptr.base = (u32) &idt;
idt_ptr.limit = IDT_ENTRIES * sizeof(idt_gate_t) - 1;
/* Don't make the mistake of loading &idt -- always load &idt_reg */
__asm__ __volatile__("lidtl (%0)" : : "r" (&idt_ptr));
}

27
src/kernel/platform/interrupts/idt.h
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@ -1,27 +0,0 @@
#ifndef IDT_H
#define IDT_H
#include "../types.h"
#define KERNEL_CS 0x08
#define IDT_ENTRIES 256
// An entry in the IDT
typedef struct {
u16 low_offset; // Low 16 bits of handler address
u16 sel; // Kernel code segment selector
u8 reserved; // Always zero
u8 flags; // x xx x xxxx, Present, ring, type, 1110 = "32bit int gate"
u16 high_offset; // High 16 bits of handler address
} __attribute__((packed)) idt_gate_t;
// The IDT itself
typedef struct {
u16 limit;
u32 base;
} __attribute__((packed)) idt_pointer_t;
void idt_set_gate(int n, u32 handler_addr);
void idt_set();
#endif

286
src/kernel/platform/interrupts/int.asm
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@ -1,286 +0,0 @@
; in isr.c
[extern isr_handler]
isr_common_stub:
; Save CPU state
pusha ; Pushes edi,esi,ebp,esp,ebx,edx,ecx,eax
mov ax, ds ; Lower 16-bits of eax = ds.
push eax ; save the data segment descriptor
mov ax, 0x10 ; kernel data segment descriptor
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
; Call C handler
call isr_handler
; Restore CPU state
pop eax
mov ds, ax
mov es, ax
mov fs, ax
mov gs, ax
popa
add esp, 8 ; Cleans up the pushed error code and pushed ISR number
sti
iret ; pops 5 things at once: CS, EIP, EFLAGS, SS, and ESP
; We don't get information about which interrupt was caller
; when the handler is run, so we will need to have a different handler
; for every interrupt.
; Furthermore, some interrupts push an error code onto the stack but others
; don't, so we will push a dummy error code for those which don't, so that
; we have a consistent stack for all of them.
; First make the ISRs global
global isr00
global isr01
global isr02
global isr03
global isr04
global isr05
global isr06
global isr07
global isr08
global isr09
global isr10
global isr11
global isr12
global isr13
global isr14
global isr15
global isr16
global isr17
global isr18
global isr19
global isr20
global isr21
global isr22
global isr23
global isr24
global isr25
global isr26
global isr27
global isr28
global isr29
global isr30
global isr31
; 0: Divide By Zero Exception
isr00:
cli
push byte 0
push byte 0
jmp isr_common_stub
; 1: Debug Exception
isr01:
cli
push byte 0
push byte 1
jmp isr_common_stub
; 2: Non Maskable Interrupt Exception
isr02:
cli
push byte 0
push byte 2
jmp isr_common_stub
; 3: Int 3 Exception
isr03:
cli
push byte 0
push byte 3
jmp isr_common_stub
; 4: INTO Exception
isr04:
cli
push byte 0
push byte 4
jmp isr_common_stub
; 5: Out of Bounds Exception
isr05:
cli
push byte 0
push byte 5
jmp isr_common_stub
; 6: Invalid Opcode Exception
isr06:
cli
push byte 0
push byte 6
jmp isr_common_stub
; 7: Coprocessor Not Available Exception
isr07:
cli
push byte 0
push byte 7
jmp isr_common_stub
; 8: Double Fault Exception (With Error Code!)
isr08:
cli
push byte 8
jmp isr_common_stub
; 9: Coprocessor Segment Overrun Exception
isr09:
cli
push byte 0
push byte 9
jmp isr_common_stub
; 10: Bad TSS Exception (With Error Code!)
isr10:
cli
push byte 10
jmp isr_common_stub
; 11: Segment Not Present Exception (With Error Code!)
isr11:
cli
push byte 11
jmp isr_common_stub
; 12: Stack Fault Exception (With Error Code!)
isr12:
cli
push byte 12
jmp isr_common_stub
; 13: General Protection Fault Exception (With Error Code!)
isr13:
cli
push byte 13
jmp isr_common_stub
; 14: Page Fault Exception (With Error Code!)
isr14:
cli
push byte 14
jmp isr_common_stub
; 15: Reserved Exception
isr15:
cli
push byte 0
push byte 15
jmp isr_common_stub
; 16: Floating Point Exception
isr16:
cli
push byte 0
push byte 16
jmp isr_common_stub
; 17: Alignment Check Exception
isr17:
cli
push byte 0
push byte 17
jmp isr_common_stub
; 18: Machine Check Exception
isr18:
cli
push byte 0
push byte 18
jmp isr_common_stub
; 19: Reserved
isr19:
cli
push byte 0
push byte 19
jmp isr_common_stub
; 20: Reserved
isr20:
cli
push byte 0
push byte 20
jmp isr_common_stub
; 21: Reserved
isr21:
cli
push byte 0
push byte 21
jmp isr_common_stub
; 22: Reserved
isr22:
cli
push byte 0
push byte 22
jmp isr_common_stub
; 23: Reserved
isr23:
cli
push byte 0
push byte 23
jmp isr_common_stub
; 24: Reserved
isr24:
cli
push byte 0
push byte 24
jmp isr_common_stub
; 25: Reserved
isr25:
cli
push byte 0
push byte 25
jmp isr_common_stub
; 26: Reserved
isr26:
cli
push byte 0
push byte 26
jmp isr_common_stub
; 27: Reserved
isr27:
cli
push byte 0
push byte 27
jmp isr_common_stub
; 28: Reserved
isr28:
cli
push byte 0
push byte 28
jmp isr_common_stub
; 29: Reserved
isr29:
cli
push byte 0
push byte 29
jmp isr_common_stub
; 30: Reserved
isr30:
cli
push byte 0
push byte 30
jmp isr_common_stub
; 31: Reserved
isr31:
cli
push byte 0
push byte 31
jmp isr_common_stub

89
src/kernel/platform/interrupts/isr.c
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@ -1,89 +0,0 @@
#include "isr.h"
#include "idt.h"
#include "../../print.h"
#include "../../util.h"
void isr_setup() {
idt_set_gate(0, (u32)isr00);
idt_set_gate(1, (u32)isr01);
idt_set_gate(2, (u32)isr02);
idt_set_gate(3, (u32)isr03);
idt_set_gate(4, (u32)isr04);
idt_set_gate(5, (u32)isr05);
idt_set_gate(6, (u32)isr06);
idt_set_gate(7, (u32)isr07);
idt_set_gate(8, (u32)isr08);
idt_set_gate(9, (u32)isr09);
idt_set_gate(10, (u32)isr10);
idt_set_gate(11, (u32)isr11);
idt_set_gate(12, (u32)isr12);
idt_set_gate(13, (u32)isr13);
idt_set_gate(14, (u32)isr14);
idt_set_gate(15, (u32)isr15);
idt_set_gate(16, (u32)isr16);
idt_set_gate(17, (u32)isr17);
idt_set_gate(18, (u32)isr18);
idt_set_gate(19, (u32)isr19);
idt_set_gate(20, (u32)isr20);
idt_set_gate(21, (u32)isr21);
idt_set_gate(22, (u32)isr22);
idt_set_gate(23, (u32)isr23);
idt_set_gate(24, (u32)isr24);
idt_set_gate(25, (u32)isr25);
idt_set_gate(26, (u32)isr26);
idt_set_gate(27, (u32)isr27);
idt_set_gate(28, (u32)isr28);
idt_set_gate(29, (u32)isr29);
idt_set_gate(30, (u32)isr30);
idt_set_gate(31, (u32)isr31);
idt_set();
}
char *exception_messages[] = {
"Division By Zero",
"Debug",
"Non Maskable Interrupt",
"Breakpoint",
"Into Detected Overflow",
"Out of Bounds",
"Invalid Opcode",
"No Coprocessor",
"Double Fault",
"Coprocessor Segment Overrun",
"Bad TSS",
"Segment Not Present",
"Stack Fault",
"General Protection Fault",
"Page Fault",
"Unknown Interrupt",
"Coprocessor Fault",
"Alignment Check",
"Machine Check",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved",
"Reserved"
};
void isr_handler(registers_t r) {
print_str("int: ");
char s[3];
int_to_ascii(r.int_no, s);
print_str(s);
print_str("\n");
print_str(exception_messages[r.int_no]);
print_str("\n");
}

48
src/kernel/platform/interrupts/isr.h
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@ -1,48 +0,0 @@
#pragma once
#include "../types.h"
typedef struct {
u32 ds; // Data segment selector
u32 edi, esi, ebp, esp, ebx, edx, ecx, eax; // Pushed by pusha
u32 int_no, err_code; // Interrupt number and error code (if present)
u32 eip, cs, eflags, useresp, ss; // Pushed automatically by the CPU
} registers_t;
// CPU exception interrupts
// ^ - pushes error code
extern void isr00(); // Division by Zero
extern void isr01(); // Debug Exception
extern void isr02(); // Non Maskable Interrupt
extern void isr03(); // Breakpoint
extern void isr04(); // Into detected overflow?
extern void isr05(); // Out of Bounds
extern void isr06(); // Invalid opcode
extern void isr07(); // No coprocessor
extern void isr08(); //^ Double fault
extern void isr09(); // Coprocessor segment overrun
extern void isr10(); //^ Bad TSS
extern void isr11(); //^ Segment not present
extern void isr12(); //^ Stack fault
extern void isr13(); //^ General Protection Fault
extern void isr14(); //^ Page Fault
extern void isr15(); // Unknown Interrupt
extern void isr16(); // Coprocessor Fault
extern void isr17(); // Alignment check exception
extern void isr18(); // Machine check exception
extern void isr19(); // Reserved
extern void isr20(); // Reserved
extern void isr21(); // Reserved
extern void isr22(); // Reserved
extern void isr23(); // Reserved
extern void isr24(); // Reserved
extern void isr25(); // Reserved
extern void isr26(); // Reserved
extern void isr27(); // Reserved
extern void isr28(); // Reserved
extern void isr29(); // Reserved
extern void isr30(); // Reserved
extern void isr31(); // Reserved
void isr_setup();
void isr_handler(registers_t r);